کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / ششمین کنفرانس بین المللی میکروالکترونیک ایران

A runtime reconfigurable exact-approximate full-adder design

نویسندگان :

Keihan Naseri¹ Hadi Jahanirad²

1- دانشگاه کردستان 2- دانشگاه کردستان

کلمات کلیدی :

Full Adders،approximate computing،re-configurable design،transistor-level design

چکیده :

Approximate arithmetic modules are attractive solution to save power consumption in error resilience applications. Full-adder (FA) as the core-computing module contributes major part of arithmetic modules in digital systems. However, designing the FA module to be applied in both approximate and exact modes would become a major goal in low-power integrated circuits design. In this paper, we present a new configurable FA with runtime configurability between exact and approximate modes at the transistor level. The configurability of the proposed FA achieves using embedded switches in the internal nodes of the circuit. Our circuit provides an output accuracy of 6 in approximate mode. We implemented our adder using GPDK 45-nm technology node and evaluated it by Cadence virtuoso. Our proposed adder consumes 23% lesser power compared to the Mirror Adder when operating in approximate mode.

لیست مقالات

لیست مقالات بایگانی شده

Optimizing High Dynamic Range Current Measurement Circuit for IoT Applications

Yas Hosseini Tehrani - ُSeyed Mojtaba Atarodi

Modeling GaN-HEMT Electrostatic Band Diagram under full depletion approximation

Behnam Jafari Touchaei - Majid Shalchian

Enhanced sensitivity of ISFET pH-sensor utilizing reduced Graphene Oxide

Hossein Rezaei Estakhroyeh - Mahdiyeh Mehran - Esmat Rashedi

Frequency Response and Design Based on gm/ID of Amplifier in CNFET Technology

S. Mohammadali Zanjani - Mehdi Dolatshahi - Massoud Dousti - Zahra Alaie - Ata Jahangir Moshayedi - Arash Mehrabi

طراحی و شبیه‌سازی جمع کننده 64 بیتی سریع با استفاده از ترانزیستورهای نانو لوله کربنی (CNTFET)

علیرضا جعفری تازه کند - جواد جاویدان

Design of a Calibration Circuit for Adaptive Phase-Locked Loop in the 5GHz Range Using CMOS 180nm Technology

Reza MirAlvandi - Mahdi Ehsanian

Optimized design of Lower Complexity Reversible Toffoli Gate in QCA Technology

Saeid Seyedi - Hatam Abdoli

Design and Performance Analysis of a Diplexer for Simultaneous GSM and Bluetooth Communication

Hamid Rahimpour - Sajjad Mohammadian - Reza Nemati

A 0.9-8 GHz Highly Linear SAW-Less Direct-Conversion Receiver Front-End for 5G Communication Standard

Erfan Salighe - Mortaza Mojarad

Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units

Maedeh Ghaderi - Arvin Delavari - Faraz Ghoreishy - Sattar Mirzakuchaki

بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 41.5.5