0% Complete
صفحه اصلی
/
هفتمین کنفرانس بین المللی میکروالکترونیک ایران
A 10-bit, 110-MS/s Synchronous SAR ADC Using a Split‑DAC Architecture with the new comparator
نویسندگان :
Sajjad Ali Abbasi Yaghmourali
1
Morteza Mousazadeh
2
1- دانشگاه ارومیه
2- دانشگاه ارومیه
کلمات کلیدی :
SAR ADC،Split DAC،Comparator،Bootstrapped Switch،Synchronous control logic،CMOS
چکیده :
Abstract—This paper presents the design of a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) operating at a sampling rate of 110 MS/s. The circuit is implemented using a synchronous architecture. To achieve this high-speed performance, key design considerations include the selection and optimization of a high-performance comparator, the implementation of an efficient sampling network, and the adoption of a novel synchronous switching scheme. The proposed ADC achieves an effective number of bits (ENOB) of 9.4 at the Nyquist rate.
لیست مقالات
لیست مقالات بایگانی شده
High Figure of Merit Metasurface Biosensor at Optical Telecommunication Band
Hemin Ebrahimi - Keyhan Hosseini - Mohammad Razaghi
Investigation of Surface Plasmon Resonance and Light Scattering by Gold Nanoparticles in Air and Dielectric Environments
Habib Khoshsima - Reza Morsali
Neural networks & logistic regression for FPGA hardware trojan detection
Milad Pazira - Yasser Baleghi - Mohammad-Ali Mahmoodpour
Design of a High-Efficiency Deep Bias Class-AB Power Amplifier With 70% PAE at P1dB
Fazel Ziraksaz - Alireza Hassanzadeh
A Low-Noise Amplifier with Bandwidth Extension and Noise Cancellation for 5G Receivers
Pardis Javanbakht - Mortaza Mojarad
Graphene-Based Ring Resonator Ammonia Sensor: Design Optimization for Maximum Sensitivity and Q-Factor
Raheleh Masoumi - Manouchehr Bahrami
Double-OTA External Capless Low-power LDO Regulator with Enhanced PSR and Transient Response
Mohammad Ahmadi - Emad Ebrahimi
New Method to Enhance Power Amplifier Efficiency Using Envelope Tracking for the 5G Standard
Alireza Naghilou - Morteza Mousazadeh
Enhanced sensitivity of ISFET pH-sensor utilizing reduced Graphene Oxide
Hossein Rezaei Estakhroyeh - Mahdiyeh Mehran - Esmat Rashedi
Circuit Analysis and Design of a Low-Noise SiGe:C HBT Amplifier with Enhanced Input Matching
Sedighe Babaei Sedaghat - Mortaza Mojarad - Fateme Zadehpariza
بیشتر
ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 44.5.0
