کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

A 10-bit, 110-MS/s Synchronous SAR ADC Using a Split‑DAC Architecture with the new comparator

نویسندگان :

Sajjad Ali Abbasi Yaghmourali¹ Morteza Mousazadeh²

1- دانشگاه ارومیه 2- دانشگاه ارومیه

کلمات کلیدی :

SAR ADC،Split DAC،Comparator،Bootstrapped Switch،Synchronous control logic،CMOS

چکیده :

Abstract—This paper presents the design of a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) operating at a sampling rate of 110 MS/s. The circuit is implemented using a synchronous architecture. To achieve this high-speed performance, key design considerations include the selection and optimization of a high-performance comparator, the implementation of an efficient sampling network, and the adoption of a novel synchronous switching scheme. The proposed ADC achieves an effective number of bits (ENOB) of 9.4 at the Nyquist rate.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 42.5.4