کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

Design of a Compact Approximate Multiplier in QCA Technology Using a Three-Layer Architecture

نویسندگان :

Saeid Seyedi¹ Hatam Abdoli²

1- دانشگاه بوعلی سینا 2- دانشگاه بوعلی سینا

کلمات کلیدی :

QCA،Approximate،Multilayer Design،Low-Power

چکیده :

Since every mature technology in the physical world is approaching its scaling limitations, a new paradigm for computing will have to be developed to keep performance and efficiency on the increase. CMOS technology, the source of modern VLSI systems, faces tremendous challenges with device scaling in the nanometer range. Quantum-dot Cellular Automata (QCA) has been explored as a viable substitute, offering ultra-high-density devices, ultra-low power usage, and high-speed computations. Multiplication is among the most power-consuming operations in digital circuits. In most error-resilient applications, compromising on a small loss in accuracy for enormous power and area savings can lead to significant system-level benefits. This paper proposes a novel approximate QCA-based multiplier based on a three-layer (multilayer) architecture to have minimal wire crossings and reduced critical path delay. With strategic partial product generation reduction and compression, the architecture is simplified at the expense of no acceptable computation precision. The architecture is realized with 65 QCA cells on a 0.07 µm² surface area, with one clock cycle (4/4 phases) latency. It exhibits an average energy dissipation of 3.02 eV and a total energy of 3.32 eV in QCADesigner-E simulations. The result confirms that accuracy relaxation under control can lead to considerable power and area reduction, making the proposed multiplier a viable candidate for fault-tolerant nanoscale systems with low power and high throughput.