کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

An Improved 8-Bit Flash ADC Evaluated with Histogram-Based Error Detection Concept

نویسندگان :

Seyed Mohammadreza Heydarian¹ Nabiollah Shiri²

1- دانشگاه آزاد اسلامی واحد شیراز 2- دانشگاه آزاد اسلامی واحد شیراز

کلمات کلیدی :

flash ADC،comparator،histogram،resistor ladder،encoder،error detection

چکیده :

Flash analog-to-digital converters (ADCs) are applicable in high-speed systems. Despite their advantages, flash ADCs suffer from differential nonlinearity (DNL) and integral nonlinearity (INL), bubble errors, and high-power consumption. To address these issues, in this paper, the encoder part of an 8-bit flash ADC is simplified by a NOT-AND-OR series of digital gates. Then, various errors are applied, and a histogram-based error detection mechanism is introduced, which presents ADC errors considering the distribution of codes in the digital-to-analog converter (DAC) output. The presented 8-bit flash ADC is implemented using 90 nm CMOS technology. The comparator offsets and other imperfections regarding the resistor ladder are applied, and the capability of the histogram-based method is approved for an error detection mechanism. Simulation results for a normal operation of the presented flash ADC at a sampling rate of 1 GHz demonstrate an INL of 0.987 LSB (least-significant-bit), DNL of 0.165 LSB, an effective number of bits (ENOB) of 7.473, a power consumption of 63.141 μW, and an energy efficiency figure of merit (FoM) of 0.353 fJ/step. As performed in this research, by integrating low-power design strategies and further optimization, the flash ADC performance is improved, making it more suitable for modern high-speed, high-accuracy applications.