کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

High-Speed Approximate Addition with Half Adder-Based Multi-Stage Architecture

نویسندگان :

Haniyeh Bazleh¹ Hadiseh Babazadeh²

1- Urmia University of Technology 2- Urmia University of Technology

کلمات کلیدی :

Power-Delay Product (PDP)،Propagation Delay Optimization،Error-Resilient Computing،Digital Signal Processing،Energy-Efficient Circuit

چکیده :

The growing demand for energy-efficient and high-performance computing has motivated the exploration of approximate arithmetic circuits, particularly adders, for error-tolerant applications. This work presents a novel approximate adder architecture that leverages half adders (HAs) in place of conventional full adders (FAs) to reduce delay, area, and power consumption. The proposed design employs a multi-stage structure in which sum and carry signals are progressively generated and propagated, with the final carry output obtained by merging stage-wise carry signals through an OR gate. Simulation results for an 8-bit configuration in a 0.18 μm CMOS process demonstrate a trade-off between accuracy and efficiency: a three-stage design achieves a 12.24% error rate with a 50% reduction in delay and the lowest power-delay product (148.314 fWs), while a four-stage design improves accuracy to 5.96% with further delay reduction but increased power consumption. The results confirm that the proposed approximate adder provides a flexible solution for energy-constrained computing systems, allowing designers to balance accuracy, speed, and power according to application requirements.