کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / ششمین کنفرانس بین المللی میکروالکترونیک ایران

Design of Floating-Point Multiplier Architecture with Adaptive Data Timing Channels

نویسندگان :

Hoda Ghabeli¹

1- آزاد اسلامی کرمان

کلمات کلیدی :

Arithmetic Circuits،floating-point multiplier،multi-path mantissa processing

چکیده :

Abstract— The mantissa multiplication is a significant portion of the floating-point multiplier. In this paper, a multi-path mantissa processing (MPM) floating-point multiplier scheme is proposed. The mantissa computation path is divided into several sub-paths for higher execution speed and energy efficiency. The computation paths are considered based on the characteristics of the input data to reduce the risk of generating approximate results. Different input data can generate variable latency and data time channels. The proposed architecture includes a design of a modified 5-2 compressor for a specific range of floating-point data for utilization in a floating-point multiplier. An adaptive data time channels approach employs a controller to select the appropriate path according to the input data. The proposed design operates in parallel with the exact module and is accurate, which improves the operating speed of the entire circuit.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 41.1.2