کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

Design and Optimization of Multilayer Approximate Multipliers in QCA

نویسندگان :

Shobeir Fayazi¹ Hatam Abdoli² Saeid Seyedi³

1- دانشگاه بوعلی سینا 2- دانشگاه بوعلی سینا 3- دانشگاه بوعلی سینا

کلمات کلیدی :

QCA،Approximate Multiplier،Majority Logic،Multilayer Design،Energy Efficiency

چکیده :

VLSI systems are approaching physical scaling limits, and as device dimensions enter the deep nanoscale, short-channel effects, quantum tunneling, and leakage currents make CMOS scaling increasingly impractical. Quantum-dot Cellular Automata (QCA) has emerged as a highly promising post-CMOS technology with ultra-high density, near-zero static power, and high-speed operation exploiting electron polarization. Multiplication, as one of the most power-, area-, and delay-hungry operations in digital circuits, is a prime candidate for approximation in error-tolerant applications. This paper presents two novel QCA-based approximate multipliers (a 2×2 circuit with 44 cells in 0.0291 µm² and a 4×4 circuit with 532 cells in 0.42 µm²) that trade controlled accuracy for considerable power, delay, and area savings. Both architectures leverage majority logic with partial product modification. Structural optimizations, including multilayer routing and two-dimensional 2D clocking, are employed for wire-crossing overhead reduction and stability improvement. Circuits are proposed and simulated in QCADesigner-E with a maximum of 29% saving in power, 24% saving in delay, and 42% saving in area compared to exact QCA multipliers with a mean relative error (MRE) of less than 3%.