کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

Design and Implementation of High-Speed Vedic-Based Squarer Circuit

نویسندگان :

Zahra Ahmari¹ Behbood Mashoufi² Amir Fathi³ Mir Majid Ghasemi⁴ Golsa Taghizadeh Afshari⁵

1- Urmia University 2- Urmia University 3- Urmia University 4- Urmia University 5- Urmia University

کلمات کلیدی :

Vedic،Square root،Vedic Mathematics،Multiplier،VLSI

چکیده :

This paper presents the design and implementation of novel 2-bit, 3-bit, and 4-bit square root circuits based on the ancient Indian Vedic mathematics method. These circuits utilize key Vedic sutras and arithmetic identities to decompose and efficiently compute square roots through modular, bitwise operations. The proposed architectures extend previously reported one- and two-bit designs using the first-type square identity, enabling scalable and precise root extraction for multi-bit inputs. The superior performance of the proposed circuits, exhibiting low power consumption on the order of approximately 37.8 μwatt and minimal delay around 770 ps while maintaining accurate computation of square roots. These characteristics highlight the advantages of applying Vedic mathematical principles to digital hardware design, emphasizing reduced complexity, enhanced speed, and energy efficiency. This work provides a foundation for implementing compact, low-latency arithmetic units suitable for embedded and signal processing applications.