کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

An Area-Efficient Low-Power Frequency-Doubler Circuit Implemented on Differential VCOs

نویسندگان :

Elham Sharifi¹ Sarang Kazeminia² Keyvan Ghorbani³

1- دانشگاه صنعتی ارومیه 2- دانشگاه صنعتی ارومیه 3- دانشگاه تبریز

کلمات کلیدی :

Frequency Doubler،Frequency Synthesizer،Clock Generation،Low-Power Clock Management

چکیده :

An open-loop low-power and area-efficient frequency doubler circuit is introduced to be added on voltage-controlled delay elements. In some mixers and clock and data recovery (CDR) circuits, where phase locked loops (PLL) cannot satisfy the area and power constraints, the proposed circuit can be repeatedly used for local generation of multiples of 2N from the input frequency. The proposed frequency doubler can be implemented on a simple CMOS differential pair with complementary input clock applied to its inputs. Also, it can be applied as an add-on to voltage-controlled delay elements even in delay locked loops (DLLs) or voltage-controlled oscillators (VCO). A simple strategy is also introduced to primarily correct the duty cycle of the generated clock. Simulation results in a 180nm CMOS process at different corner conditions confirm that the frequency of input clock within the range of 10MHz-to-1.15GHz can be successfully doubled by consuming 3.8mW and 5.3mW power at 20MHz and 2.3GHz output frequencies, respectively, at 1.8Volts supply voltage. Applying the transient noise analysis, RMS jitter of the output clock reaches to 100pSec and 3.8pSec at 20MHz and 2.3GHz output frequencies, respectively.