کنفرانس بین المللی میکروالکترونیک ایران

صفحه اصلی / هفتمین کنفرانس بین المللی میکروالکترونیک ایران

Adaptive Oversampling-based CDR with Phase Correction for Low-Cost FPGAs

نویسندگان :

Amin Khalilzadegan¹ Asal Malekara² Amir Fathi³ Mir Majid Ghasemi⁴

1- دانشگاه ارومیه - دانشکده برق و کامپیوتر 2- دانشگاه ارومیه - دانشکده برق و کامپیوتر 3- دانشگاه ارومیه - دانشکده برق و کامپیوتر 4- دانشگاه ارومیه - دانشکده برق و کامپیوتر

کلمات کلیدی :

Adaptive Phase Correction،Clock and Data Recovery،Low-Cost FPGA،XOR-based Edge Detection،Oversampling-based Clock Recovery

چکیده :

This paper presents a novel method for clock and data recovery on low-cost FPGA platforms, addressing long-term frequency drift in systems lacking dedicated transceiver blocks. The approach combines oversampling with automatic phase correction to achieve reliable synchronization between the transmitter and receiver clocks. A simple XOR-based edge detection along with a 2-bit counter is employed to detect phase misalignments and adaptively correct phase drift. Since no complex analog PLL/DLL circuits or external clock lines are required, the method is well-suited for resource-constrained systems. Its performance was evaluated through simulations on the ISE software using a Verilog code and a corresponding test bench. For practical validation, an experimental setup was developed to emulate a ring network with five stations using cost-effective Xilinx Spartan-6 FPGAs, where the proposed method served as the system’s CDR mechanism. The results demonstrate the robustness of the method in handling phase drift and maintaining stable communication, making it a viable option for various applications.